SCI LincChip™ Technology

SCI has been earning increasing acceptance in the industry, which has created a demand for low cost SCI interface.

ISS has developed LincChip™ technology to meet this need.

LincChip technology consists of a design library with a variety of interoperable low-gate-count building blocks, that can be combined to make SCI interfaces ranging from general-purpose I/O through networking up to cache-coherent multiprocessor interconnects.

The modular LincChip approach allows the cost of chip development to be spread over a wide range of applications. The low gate count enabled by SCI's RISC-like protocols allows these LincChip designs to be integrated with other application-specific functions in a single ASIC device that even includes the transceivers. The low gate counts also make it easy to implement fault-tolerant or multidimensional SCI systems by adding additional SCI connections on the same chip.

The LincChip will drive low-cost readily available cable-connectors of up to 30 meters long quite comfortably with the on chip transceivers without need for any external components.

LincChip Components

The LincChip provides two major components:

	LincCore™.
	HostCtl™.

The LincCore is responsible for managing all functions related to the interface with SCI. The HostCtl provides a back-end bi-directional bus interface, which implements a peer-to-peer 64-bit interface. Typically, a node will interface to this back-end bus to provide access to the packet for upper-layer protocols.

LincChip-8™ Features

Implements SCI packet transport layer.

Built-in routing support.

LincCore offers true SCI standard compliance,

	Automatic ringlet initialization, no external support.
	Fully featured SCI elasticity, no centralized clock.

Concurrent maintenance of virtual channels,

Deadlock free non-blocking operation.

Design supports upto 4 concurrent packets per virtual channel,

	Concurrency at the transport layer.
	Elasticity between application and transport
	Application does not adversely affect transport layer.

Multiple LincCores can be used to improve,

	Connectivity.
	Bandwidth.

8 bit data + 2 control signal for SCI connection,

	On chip differential I/O transceivers.
	Emerging low cost DC coupled 10-bit parallel fibre technology capable.

Lightweight,

	LincCore-8 is 20-25K functional gates excluding RAMs.
	System requirement dictates the size of the packet buffer RAM.

High Performance,

	SCI fabric interface currently delivers 100 megabytes per second incoming and outgoing bandwidth very comfortably with current mainstream half micron CMOS technology.
	Quarter micron CMOS provides improved bandwidth of 200 megabytes per second.

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